From vkowalski@berkeley.edu Wed Nov 22 09:42:08 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!berkeley!vkowalski From: vkowalski@berkeley.edu (Valeria Kowalski) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Nov22.094208.3793@berkeley.edu> Date: Wed, 22 Nov 1995 09:42:08 GMT Organization: UC Berkeley Department of EECS NNTP-Posting-Host: berkeley.edu X-Newsreader: WinVN 0.99.5 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Valeria Kowalski SupraFAXModem 28.8 @ 33,600 bps "5 sigma is a discovery. 7 is a question." From bhughes@pipeline.com Thu Nov 23 06:32:08 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!pipeline!bhughes From: bhughes@pipeline.com (Bill Hughes) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Nov23.063208.5821@pipeline.com> Date: Thu, 23 Nov 1995 06:32:08 GMT References: <1995Nov22.094208.3793@berkeley.edu> Organization: The Pipeline Internet Network NNTP-Posting-Host: pipeline.com X-Newsreader: TIN [version 1.2 PL2] Lines: 8 In article <1995Nov22.094208.3793@berkeley.edu>, vkowalski@berkeley.edu (Valeria Kowalski) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Bill Hughes Tape trading list upon request. SASE required for international mail. From anilsson@tum.de Sat Nov 25 00:47:08 1995 Path: ashpoly!cascade!bigsur!tum!anilsson From: anilsson@tum.de (Anja Nilsson) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Nov25.004708.2495@tum.de> Date: Sat, 25 Nov 1995 00:47:08 GMT References: <1995Nov22.094208.3793@berkeley.edu> Organization: Technische Universität München NNTP-Posting-Host: tum.de X-Newsreader: Netscape 1.1N Lines: 9 In article <1995Nov22.094208.3793@berkeley.edu>, vkowalski@berkeley.edu (Valeria Kowalski) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. -- Anja Nilsson -- Technische Universität München "Measuring a record you own is listening, not piracy."