From mmartinez@kiae.su Mon Apr 17 17:32:56 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!kiae!mmartinez From: mmartinez@kiae.su (Mathieu Martínez) Newsgroups: comp.sys.m68k Subject: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr17.173256.3188@kiae.su> Date: Mon, 17 Apr 1995 17:32:56 GMT Organization: Kurchatov Institute of Atomic Energy, Moscow NNTP-Posting-Host: kiae.su X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Mathieu Martínez *PLONK* filter active for trolls. Sun SparcStation 20 - NetBSD 1.0 From trobertson@kth.se Wed Apr 19 10:43:56 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!kth!trobertson From: trobertson@kth.se (Tyler Robertson) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr19.104356.6414@kth.se> Date: Wed, 19 Apr 1995 10:43:56 GMT References: <1995Apr17.173256.3188@kiae.su> Organization: Royal Institute of Technology, Stockholm NNTP-Posting-Host: kth.se X-Newsreader: Netscape 1.1N Lines: 9 In article <1995Apr17.173256.3188@kiae.su>, mmartinez@kiae.su (Mathieu Martínez) writes: > Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- === Tyler Robertson === Dept of Electrical Engineering, Royal Institute of Technology, Stockholm "They will send a copy in my place." From smacdonald@u-tokyo.ac.jp Thu Apr 20 06:07:56 1995 Path: ashpoly!cascade!brgate!saturno!u-tokyo!smacdonald From: smacdonald@u-tokyo.ac.jp (Seo-yeon MacDonald) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr20.060756.9316@u-tokyo.ac.jp> Date: Thu, 20 Apr 1995 06:07:56 GMT References: <1995Apr17.173256.3188@kiae.su> <1995Apr19.104356.6414@kth.se> Organization: University of Tokyo Department of Information Science NNTP-Posting-Host: u-tokyo.ac.jp X-Newsreader: Netscape 1.1N Lines: 9 In article <1995Apr19.104356.6414@kth.se>, trobertson@kth.se (Tyler Robertson) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- === Seo-yeon MacDonald === Dept of Electrical Engineering, University of Tokyo Department of Information Science "Extraordinary claims require extraordinary spectra." From llindqvist@unam.mx Fri Apr 21 00:45:56 1995 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!unam!llindqvist From: llindqvist@unam.mx (Liam Lindqvist) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr21.004556.4299@unam.mx> Date: Fri, 21 Apr 1995 00:45:56 GMT References: <1995Apr17.173256.3188@kiae.su> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: NewsWatcher 2.0b24 Lines: 10 In article <1995Apr17.173256.3188@kiae.su>, mmartinez@kiae.su (Mathieu Martínez) writes: > Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Liam Lindqvist *PLONK* filter active for trolls. Atari Falcon 030 - NetBSD 1.0