From elindqvist@hanse.de Tue Jul 04 02:06:59 1995 Path: ashpoly!cascade!brgate!saturno!hanse!elindqvist From: elindqvist@hanse.de (Elaine Lindqvist) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jul04.020659.2108@hanse.de> Date: Tue, 04 Jul 1995 02:06:59 GMT Organization: Hanse-Netzwerk Hamburg NNTP-Posting-Host: hanse.de X-Newsreader: WinVN 0.99.5 Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Elaine Lindqvist -- Hanse-Netzwerk Hamburg "Hardware is temporary. The signal survives." From ccampbell@uu.net Wed Jul 05 07:21:59 1995 Path: ashpoly!cascade!mxgate!coyoacan!uu!ccampbell From: ccampbell@uu.net (Camila Campbell) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jul05.072159.4203@uu.net> Date: Wed, 05 Jul 1995 07:21:59 GMT References: <1995Jul04.020659.2108@hanse.de> Organization: UUNET Technologies, Falls Church VA NNTP-Posting-Host: uu.net X-Newsreader: Netscape 1.1N Lines: 10 In article <1995Jul04.020659.2108@hanse.de>, elindqvist@hanse.de (Elaine Lindqvist) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. -- Camila Campbell "5 sigma is a discovery. 7 is a question." Macintosh IIfx / AmigaOS 3.1 From lpopov@mit.edu Wed Jul 05 14:23:59 1995 Path: ashpoly!cascade!brgate!saturno!mit!lpopov From: lpopov@mit.edu (Lisa Popov) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jul05.142359.3236@mit.edu> Date: Wed, 05 Jul 1995 14:23:59 GMT References: <1995Jul04.020659.2108@hanse.de> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: WinVN 0.99.5 Lines: 9 In article <1995Jul04.020659.2108@hanse.de>, elindqvist@hanse.de (Elaine Lindqvist) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Lisa Popov US Robotics Courier V.34 @ 19,200 bps "The carrier frequency does not drift by accident." From stakahashi@mit.edu Fri Jul 07 09:28:59 1995 Path: ashpoly!cascade!brgate!saturno!mit!stakahashi From: stakahashi@mit.edu (Steve Takahashi) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jul07.092859.5380@mit.edu> Date: Fri, 07 Jul 1995 09:28:59 GMT References: <1995Jul04.020659.2108@hanse.de> <1995Jul05.142359.3236@mit.edu> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: Netscape 1.1N Lines: 8 In article <1995Jul05.142359.3236@mit.edu>, lpopov@mit.edu (Lisa Popov) writes: > Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. -- Steve Takahashi Tape trading list upon request. SASE required for international mail. From awatanabe@unam.mx Sat Jul 08 07:30:59 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!unam!awatanabe From: awatanabe@unam.mx (Anja Watanabe) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jul08.073059.1627@unam.mx> Date: Sat, 08 Jul 1995 07:30:59 GMT References: <1995Jul04.020659.2108@hanse.de> <1995Jul05.142359.3236@mit.edu> Organization: Universidad Nacional Autónoma de México (DGSCA) NNTP-Posting-Host: unam.mx X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1995Jul05.142359.3236@mit.edu>, lpopov@mit.edu (Lisa Popov) writes: > Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Anja Watanabe | awatanabe@unam.mx PGP Key fingerprint: AAE6 299D 6933 83F7 "Keep the channels open."