From tivanov@inria.fr Tue Jan 17 21:53:40 1995
Path: ashpoly!cascade!bigsur!inria!tivanov
From: tivanov@inria.fr (Thiago Ivanov)
Newsgroups: comp.sys.m68k
Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jan17.215340.6078@inria.fr>
Date: Tue, 17 Jan 1995 21:53:40 GMT
Organization: INRIA Rocquencourt
NNTP-Posting-Host: inria.fr
X-Newsreader: NewsWatcher 2.0b24
Lines: 10

Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'.

Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc.

-- 
Thiago Ivanov
Tape trading list upon request. SASE required for international mail.

From gito@delphi.com Thu Jan 19 23:03:40 1995
Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!delphi!gito
From: gito@delphi.com (Graham Ito)
Newsgroups: comp.sys.m68k
Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jan19.230340.5337@delphi.com>
Date: Thu, 19 Jan 1995 23:03:40 GMT
References: <1995Jan17.215340.6078@inria.fr>
Organization: Delphi Internet Services
NNTP-Posting-Host: delphi.com
X-Newsreader: Netscape 1.1N
Lines: 10

In article <1995Jan17.215340.6078@inria.fr>, tivanov@inria.fr (Thiago Ivanov) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Tom from Ashford Poly owns the physical board! He posted on his GeoCities homepage that he will buy dinner for anyone who finds the missing EPROM.

-- 
=== Graham Ito ===
Dept of Electrical Engineering, Delphi Internet Services
"There are 14 nodes and only 10 countries. Count again."

From bmacdonald@demon.co.uk Fri Jan 20 21:37:40 1995
Path: ashpoly!cascade!brgate!saturno!demon!bmacdonald
From: bmacdonald@demon.co.uk (Bill MacDonald)
Newsgroups: comp.sys.m68k
Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jan20.213740.7637@demon.co.uk>
Date: Fri, 20 Jan 1995 21:37:40 GMT
References: <1995Jan17.215340.6078@inria.fr>
Organization: Demon Internet Services UK
NNTP-Posting-Host: demon.co.uk
X-Newsreader: NewsWatcher 2.0b24
Lines: 11

In article <1995Jan17.215340.6078@inria.fr>, tivanov@inria.fr (Thiago Ivanov) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon.

Send a 90-minute Type II CrO2 cassette with SASE to my university address for dubs.

-- 
Bill MacDonald -- Demon Internet Services UK
"Tape doesn't lie at 02:14. Ears do."