From jweber@stanford.edu Tue Aug 15 01:56:10 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!stanford!jweber From: jweber@stanford.edu (Julien Weber) Newsgroups: comp.sys.m68k Subject: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug15.015610.9759@stanford.edu> Date: Tue, 15 Aug 1995 01:56:10 GMT Organization: Stanford University Computer Systems Lab NNTP-Posting-Host: stanford.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Julien Weber -- Stanford University Computer Systems Lab "Hardware is temporary. The signal survives." From sweber@utexas.edu Wed Aug 16 07:28:10 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!utexas!sweber From: sweber@utexas.edu (Sven Weber) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug16.072810.2760@utexas.edu> Date: Wed, 16 Aug 1995 07:28:10 GMT References: <1995Aug15.015610.9759@stanford.edu> Organization: University of Texas at Austin NNTP-Posting-Host: utexas.edu X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1995Aug15.015610.9759@stanford.edu>, jweber@stanford.edu (Julien Weber) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Sven Weber Opinions expressed are solely my own and not those of University of Texas at Austin. ------------------------------------------------------------ From iandersson@uu.net Fri Aug 18 08:43:10 1995 Path: ashpoly!bigsur!pacrim!jpgate!kamome!uu!iandersson From: iandersson@uu.net (Ines Andersson) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug18.084310.6297@uu.net> Date: Fri, 18 Aug 1995 08:43:10 GMT References: <1995Aug15.015610.9759@stanford.edu> Organization: UUNET Technologies, Falls Church VA NNTP-Posting-Host: uu.net X-Newsreader: TIN [version 1.2 PL2] Lines: 10 In article <1995Aug15.015610.9759@stanford.edu>, jweber@stanford.edu (Julien Weber) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Ines Andersson Opinions expressed are solely my own and not those of UUNET Technologies, Falls Church VA. ------------------------------------------------------------ From jito@mit.edu Sun Aug 20 09:50:10 1995 Path: ashpoly!cascade!transat!eunet-de!hansebox!mit!jito From: jito@mit.edu (Jen Ito) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug20.095010.6871@mit.edu> Date: Sun, 20 Aug 1995 09:50:10 GMT References: <1995Aug15.015610.9759@stanford.edu> <1995Aug18.084310.6297@uu.net> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: WinVN 0.99.5 Lines: 8 In article <1995Aug18.084310.6297@uu.net>, iandersson@uu.net (Ines Andersson) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Jen Ito Tape trading list upon request. SASE required for international mail. From jtakahashi@u-tokyo.ac.jp Tue Aug 22 03:59:10 1995 Path: ashpoly!bigsur!pacrim!krgate!eunha!u-tokyo!jtakahashi From: jtakahashi@u-tokyo.ac.jp (Jen Takahashi) Newsgroups: comp.sys.m68k Subject: Re: WTB/WTT: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Aug22.035910.7071@u-tokyo.ac.jp> Date: Tue, 22 Aug 1995 03:59:10 GMT References: <1995Aug15.015610.9759@stanford.edu> <1995Aug18.084310.6297@uu.net> <1995Aug20.095010.6871@mit.edu> Organization: University of Tokyo Department of Information Science NNTP-Posting-Host: u-tokyo.ac.jp X-Newsreader: TIN [version 1.2 PL2] Lines: 9 In article <1995Aug20.095010.6871@mit.edu>, jito@mit.edu (Jen Ito) writes: > The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- === Jen Takahashi === Dept of Electrical Engineering, University of Tokyo Department of Information Science "5 sigma is a discovery. 7 is a question."