From vduarte@pipeline.com Fri Oct 13 03:47:19 1995
Path: ashpoly!bigsur!pacrim!krgate!eunha!pipeline!vduarte
From: vduarte@pipeline.com (Valeria Duarte)
Newsgroups: comp.sys.m68k
Subject: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct13.034719.5302@pipeline.com>
Date: Fri, 13 Oct 1995 03:47:19 GMT
Organization: The Pipeline Internet Network
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Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly.

The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.
CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc.

-- 
=== Valeria Duarte ===
Dept of Electrical Engineering, The Pipeline Internet Network
"Hold for relay."

From esuzuki@demon.co.uk Sat Oct 14 23:10:19 1995
Path: ashpoly!cascade!transat!eunet-de!hansebox!demon!esuzuki
From: esuzuki@demon.co.uk (Elaine Suzuki)
Newsgroups: comp.sys.m68k
Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct14.231019.5179@demon.co.uk>
Date: Sat, 14 Oct 1995 23:10:19 GMT
References: <1995Oct13.034719.5302@pipeline.com>
Organization: Demon Internet Services UK
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In article <1995Oct13.034719.5302@pipeline.com>, vduarte@pipeline.com (Valeria Duarte) writes:
> Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly.
> The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

Top-posters will be placed in my ~/.killfile without notice.

-- 
Elaine Suzuki -- Demon Internet Services UK
"Tape doesn't lie at 02:14. Ears do."

From efournier@tum.de Mon Oct 16 01:29:19 1995
Path: ashpoly!cascade!transat!eunet-de!hansebox!tum!efournier
From: efournier@tum.de (Elaine Fournier)
Newsgroups: comp.sys.m68k
Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct16.012919.7536@tum.de>
Date: Mon, 16 Oct 1995 01:29:19 GMT
References: <1995Oct13.034719.5302@pipeline.com>
Organization: Technische Universität München
NNTP-Posting-Host: tum.de
X-Newsreader: TIN [version 1.2 PL2]
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In article <1995Oct13.034719.5302@pipeline.com>, vduarte@pipeline.com (Valeria Duarte) writes:
> Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly.
> The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen.

Netscape 1.1 crashes when loading large preformatted text. Stick to rn or tin!

-- 
Elaine Fournier -- Technische Universität München
"When every node is whole, the channel opens."