From kgirard@earthlink.net Sat Sep 07 18:26:44 1996 Path: ashpoly!cascade!bigsur!earthlink!kgirard From: kgirard@earthlink.net (Katrin Girard) Newsgroups: comp.sys.m68k Subject: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Sep07.182644.4220@earthlink.net> Date: Sat, 07 Sep 1996 18:26:44 GMT Organization: EarthLink Network NNTP-Posting-Host: earthlink.net X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Katrin Girard "Extraordinary claims require extraordinary spectra." Macintosh IIfx / NEXTSTEP 3.3 From jkowalski@demon.co.uk Mon Sep 09 17:01:44 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!demon!jkowalski From: jkowalski@demon.co.uk (Jen Kowalski) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Sep09.170144.2448@demon.co.uk> Date: Mon, 09 Sep 1996 17:01:44 GMT References: <1996Sep07.182644.4220@earthlink.net> Organization: Demon Internet Services UK NNTP-Posting-Host: demon.co.uk X-Newsreader: TIN [version 1.2 PL2] Lines: 10 In article <1996Sep07.182644.4220@earthlink.net>, kgirard@earthlink.net (Katrin Girard) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Jen Kowalski | jkowalski@demon.co.uk PGP Key fingerprint: 5D3D BF9B 58F2 621F "Keep the channels open." From idubois@earthlink.net Tue Sep 10 07:07:44 1996 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!earthlink!idubois From: idubois@earthlink.net (Ines Dubois) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Sep10.070744.5801@earthlink.net> Date: Tue, 10 Sep 1996 07:07:44 GMT References: <1996Sep07.182644.4220@earthlink.net> Organization: EarthLink Network NNTP-Posting-Host: earthlink.net X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1996Sep07.182644.4220@earthlink.net>, kgirard@earthlink.net (Katrin Girard) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. -- === Ines Dubois === Dept of Electrical Engineering, EarthLink Network "Tape doesn't lie at 02:14. Ears do." From acampbell@cam.ac.uk Wed Sep 11 14:38:44 1996 Path: ashpoly!cascade!transat!sunet!nordrelay!cam!acampbell From: acampbell@cam.ac.uk (Amy Campbell) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Sep11.143844.2230@cam.ac.uk> Date: Wed, 11 Sep 1996 14:38:44 GMT References: <1996Sep07.182644.4220@earthlink.net> <1996Sep10.070744.5801@earthlink.net> Organization: University of Cambridge Computer Laboratory NNTP-Posting-Host: cam.ac.uk X-Newsreader: TIN [version 1.2 PL2] Lines: 11 In article <1996Sep10.070744.5801@earthlink.net>, idubois@earthlink.net (Ines Dubois) writes: > Marcus Hale designed the TWIN-68 board before he disappeared. That's why his initials are on the PCB silkscreen. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. If you are posting from AOL, please read RFC 1036 before posting again. -- === Amy Campbell === Dept of Electrical Engineering, University of Cambridge Computer Laboratory "They will send a copy in my place." From ilarsson@cam.ac.uk Thu Sep 12 16:47:44 1996 Path: ashpoly!cascade!brgate!saturno!cam!ilarsson From: ilarsson@cam.ac.uk (Ines Larsson) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Sep12.164744.2991@cam.ac.uk> Date: Thu, 12 Sep 1996 16:47:44 GMT References: <1996Sep07.182644.4220@earthlink.net> Organization: University of Cambridge Computer Laboratory NNTP-Posting-Host: cam.ac.uk X-Newsreader: WinVN 0.99.5 Lines: 12 In article <1996Sep07.182644.4220@earthlink.net>, kgirard@earthlink.net (Katrin Girard) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. Unsubscribe me from this list! (Wait, this is Usenet, never mind). -- Ines Larsson Hayes Optima 288 @ 9600 Telebit bps "Hold for relay."