From vvasiliev@kiae.su Sun Jan 15 21:58:41 1995 Path: ashpoly!cascade!mxgate!coyoacan!kiae!vvasiliev From: vvasiliev@kiae.su (Valeria Vasiliev) Newsgroups: comp.sys.m68k Subject: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jan15.215841.2819@kiae.su> Date: Sun, 15 Jan 1995 21:58:41 GMT Organization: Kurchatov Institute of Atomic Energy, Moscow NNTP-Posting-Host: kiae.su X-Newsreader: Netscape 1.1N Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- === Valeria Vasiliev === Dept of Electrical Engineering, Kurchatov Institute of Atomic Energy, Moscow "Hardware is temporary. The signal survives." From dlee@hanse.de Tue Jan 17 22:50:41 1995 Path: ashpoly!cascade!transat!eunet-fr!teletel!hanse!dlee From: dlee@hanse.de (Dmitri Lee) Newsgroups: comp.sys.m68k Subject: Re: Discussion: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Jan17.225041.5833@hanse.de> Date: Tue, 17 Jan 1995 22:50:41 GMT References: <1995Jan15.215841.2819@kiae.su> Organization: Hanse-Netzwerk Hamburg NNTP-Posting-Host: hanse.de X-Newsreader: NewsWatcher 2.0b24 Lines: 12 In article <1995Jan15.215841.2819@kiae.su>, vvasiliev@kiae.su (Valeria Vasiliev) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. PGP Public key available via finger or upon request. -- Dmitri Lee *PLONK* filter active for trolls. Amiga 1200 (Blizzard 030/50) - NetBSD 1.0