From avasiliev@mit.edu Tue Jan 23 01:51:02 1996 Path: ashpoly!bigsur!pacrim!jpgate!kamome!mit!avasiliev From: avasiliev@mit.edu (Aiko Vasiliev) Newsgroups: comp.sys.m68k Subject: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan23.015102.2724@mit.edu> Date: Tue, 23 Jan 1996 01:51:02 GMT Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: Netscape 1.1N Lines: 11 Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Aiko Vasiliev Zyxel U-1496E @ 14,400 bps "They will send a copy in my place." From hmoreau@mit.edu Wed Jan 24 02:11:02 1996 Path: ashpoly!bigsur!pacrim!jpgate!kamome!mit!hmoreau From: hmoreau@mit.edu (Hugo Moreau) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan24.021102.6076@mit.edu> Date: Wed, 24 Jan 1996 02:11:02 GMT References: <1996Jan23.015102.2724@mit.edu> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: TIN [version 1.2 PL2] Lines: 10 In article <1996Jan23.015102.2724@mit.edu>, avasiliev@mit.edu (Aiko Vasiliev) writes: > Managed to dump the 27256 EPROMs from the TWIN-68 Rev C board recovered from Ashford Poly. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Hugo Moreau SupraFAXModem 28.8 @ ISDN 64k bps "The hatch is open. Is anyone listening?" From ttakahashi@berkeley.edu Wed Jan 24 15:15:02 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!berkeley!ttakahashi From: ttakahashi@berkeley.edu (Takeshi Takahashi) Newsgroups: comp.sys.m68k Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Jan24.151502.7729@berkeley.edu> Date: Wed, 24 Jan 1996 15:15:02 GMT References: <1996Jan23.015102.2724@mit.edu> <1996Jan24.021102.6076@mit.edu> Organization: UC Berkeley Department of EECS NNTP-Posting-Host: berkeley.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 8 In article <1996Jan24.021102.6076@mit.edu>, hmoreau@mit.edu (Hugo Moreau) writes: > That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Takeshi Takahashi -- UC Berkeley Department of EECS "Marcus is not one man."