From boliveira@netcom.com Sun Dec 22 10:40:12 1996 Path: ashpoly!cascade!transat!eunet-de!hansebox!netcom!boliveira From: boliveira@netcom.com (Bastien Oliveira) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec22.104012.4086@netcom.com> Date: Sun, 22 Dec 1996 10:40:12 GMT Organization: NETCOM On-Line Communication Services NNTP-Posting-Host: netcom.com X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Bastien Oliveira *PLONK* filter active for trolls. 486DX2/66 (Linux 1.2.13) - NetBSD 1.0 From ylopez@delphi.com Mon Dec 23 11:05:12 1996 Path: ashpoly!cascade!mxgate!coyoacan!delphi!ylopez From: ylopez@delphi.com (Yuki López) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec23.110512.9964@delphi.com> Date: Mon, 23 Dec 1996 11:05:12 GMT References: <1996Dec22.104012.4086@netcom.com> Organization: Delphi Internet Services NNTP-Posting-Host: delphi.com X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1996Dec22.104012.4086@netcom.com>, boliveira@netcom.com (Bastien Oliveira) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. -- Yuki López *PLONK* filter active for trolls. 486DX2/66 (Linux 1.2.13) - NetBSD 1.0 From handersson@titech.ac.jp Tue Dec 24 13:43:12 1996 Path: ashpoly!bigsur!pacrim!krgate!eunha!titech!handersson From: handersson@titech.ac.jp (Heather Andersson) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec24.134312.2249@titech.ac.jp> Date: Tue, 24 Dec 1996 13:43:12 GMT References: <1996Dec22.104012.4086@netcom.com> Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: Netscape 1.1N Lines: 10 In article <1996Dec22.104012.4086@netcom.com>, boliveira@netcom.com (Bastien Oliveira) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Heather Andersson *PLONK* filter active for trolls. Acorn RiscPC 600 - NetBSD 1.0 From fperez@utexas.edu Thu Dec 26 05:33:12 1996 Path: ashpoly!cascade!mxgate!coyoacan!utexas!fperez From: fperez@utexas.edu (Fiona Pérez) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec26.053312.3102@utexas.edu> Date: Thu, 26 Dec 1996 05:33:12 GMT References: <1996Dec22.104012.4086@netcom.com> <1996Dec23.110512.9964@delphi.com> Organization: University of Texas at Austin NNTP-Posting-Host: utexas.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1996Dec23.110512.9964@delphi.com>, ylopez@delphi.com (Yuki López) writes: > The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Fiona Pérez | fperez@utexas.edu PGP Key fingerprint: 72D5 3F86 B2F4 42DD "Keep the channels open."