From emartinez@u-tokyo.ac.jp Thu Jul 06 23:28:50 1995
Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!u-tokyo!emartinez
From: emartinez@u-tokyo.ac.jp (Élodie Martínez)
Newsgroups: comp.sys.m68k
Subject: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jul06.232850.4561@u-tokyo.ac.jp>
Date: Thu, 06 Jul 1995 23:28:50 GMT
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII.

Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot?

-- 
Élodie Martínez
Opinions expressed are solely my own and not those of University of Tokyo Department of Information Science.
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From asato@ox.ac.uk Sat Jul 08 04:04:50 1995
Path: ashpoly!bigsur!pacrim!jpgate!kamome!ox!asato
From: asato@ox.ac.uk (Amy Sato)
Newsgroups: comp.sys.m68k
Subject: Re: [SPECULATION] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jul08.040450.3714@ox.ac.uk>
Date: Sat, 08 Jul 1995 04:04:50 GMT
References: <1995Jul06.232850.4561@u-tokyo.ac.jp>
Organization: Oxford University Computing Laboratory
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In article <1995Jul06.232850.4561@u-tokyo.ac.jp>, emartinez@u-tokyo.ac.jp (Élodie Martínez) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

My 14.4k connection dropped twice trying to fetch this thread. Keep articles concise!

-- 
Amy Sato -- Oxford University Computing Laboratory
"Hold for relay."