From hkuznetsov@u-tokyo.ac.jp Tue Oct 22 12:39:31 1996
Path: ashpoly!cascade!mxgate!coyoacan!u-tokyo!hkuznetsov
From: hkuznetsov@u-tokyo.ac.jp (Hugo Kuznetsov)
Newsgroups: comp.sys.m68k
Subject: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1996Oct22.123931.1616@u-tokyo.ac.jp>
Date: Tue, 22 Oct 1996 12:39:31 GMT
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.
At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII.

Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot?

-- 
Hugo Kuznetsov
Opinions expressed are solely my own and not those of University of Tokyo Department of Information Science.
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From lrobertson@mindspring.com Thu Oct 24 12:38:31 1996
Path: ashpoly!bigsur!pacrim!krgate!eunha!mindspring!lrobertson
From: lrobertson@mindspring.com (Liam Robertson)
Newsgroups: comp.sys.m68k
Subject: Re: Data: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1996Oct24.123831.3755@mindspring.com>
Date: Thu, 24 Oct 1996 12:38:31 GMT
References: <1996Oct22.123931.1616@u-tokyo.ac.jp>
Organization: MindSpring Enterprises
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In article <1996Oct22.123931.1616@u-tokyo.ac.jp>, hkuznetsov@u-tokyo.ac.jp (Hugo Kuznetsov) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

Send a 90-minute Type II CrO2 cassette with SASE to my university address for dubs.

-- 
=== Liam Robertson ===
Dept of Electrical Engineering, MindSpring Enterprises
"We don't sign stars. We build them."