From dgirard@u-tokyo.ac.jp Wed Sep 21 13:27:24 1994 Path: ashpoly!cascade!mxgate!coyoacan!u-tokyo!dgirard From: dgirard@u-tokyo.ac.jp (Dave Girard) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Sep21.132724.7858@u-tokyo.ac.jp> Date: Wed, 21 Sep 1994 13:27:24 GMT Organization: University of Tokyo Department of Information Science NNTP-Posting-Host: u-tokyo.ac.jp X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot? -- Dave Girard Practical Peripherals 14.4 @ 19,200 bps "Row 14. No joke." From nlindqvist@titech.ac.jp Thu Sep 22 05:52:24 1994 Path: ashpoly!cascade!transat!sunet!nordrelay!titech!nlindqvist From: nlindqvist@titech.ac.jp (Nadia Lindqvist) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Sep22.055224.9175@titech.ac.jp> Date: Thu, 22 Sep 1994 05:52:24 GMT References: <1994Sep21.132724.7858@u-tokyo.ac.jp> Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: NewsWatcher 2.0b24 Lines: 9 In article <1994Sep21.132724.7858@u-tokyo.ac.jp>, dgirard@u-tokyo.ac.jp (Dave Girard) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. -- Nadia Lindqvist Opinions expressed are solely my own and not those of Tokyo Institute of Technology Computer Centre. ------------------------------------------------------------