From msilva@titech.ac.jp Tue Apr 04 18:46:52 1995 Path: ashpoly!cascade!transat!ukc!fennimore!titech!msilva From: msilva@titech.ac.jp (Matthias Silva) Newsgroups: comp.sys.m68k Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr04.184652.5693@titech.ac.jp> Date: Tue, 04 Apr 1995 18:46:52 GMT Organization: Tokyo Institute of Technology Computer Centre NNTP-Posting-Host: titech.ac.jp X-Newsreader: WinVN 0.99.5 Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Matthias Silva -- Tokyo Institute of Technology Computer Centre "Tape doesn't lie at 02:14. Ears do." From fcampbell@clari.net Thu Apr 06 01:06:52 1995 Path: ashpoly!cascade!brgate!saturno!clari!fcampbell From: fcampbell@clari.net (Fiona Campbell) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1995Apr06.010652.8140@clari.net> Date: Thu, 06 Apr 1995 01:06:52 GMT References: <1995Apr04.184652.5693@titech.ac.jp> Organization: ClariNet Communications Corp NNTP-Posting-Host: clari.net X-Newsreader: TIN [version 1.2 PL2] Lines: 11 In article <1995Apr04.184652.5693@titech.ac.jp>, msilva@titech.ac.jp (Matthias Silva) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Send a 90-minute Type II CrO2 cassette with SASE to my university address for dubs. -- Fiona Campbell Opinions expressed are solely my own and not those of ClariNet Communications Corp. ------------------------------------------------------------