From dcampbell@cern.ch Mon Nov 25 18:04:54 1996
Path: ashpoly!cascade!mxgate!coyoacan!cern!dcampbell
From: dcampbell@cern.ch (Diego Campbell)
Newsgroups: comp.sys.m68k
Subject: [INFO] Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1996Nov25.180454.9409@cern.ch>
Date: Mon, 25 Nov 1996 18:04:54 GMT
Organization: European Laboratory for Particle Physics, Geneva
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Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.

The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.
Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF.

Did Marcus take the decryption EPROM with him when he left the lab?

-- 
=== Diego Campbell ===
Dept of Electrical Engineering, European Laboratory for Particle Physics, Geneva
"When every node is whole, the channel opens."

From fnakamura@mindspring.com Wed Nov 27 21:23:54 1996
Path: ashpoly!cascade!brgate!saturno!mindspring!fnakamura
From: fnakamura@mindspring.com (Fiona Nakamura)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1996Nov27.212354.1445@mindspring.com>
Date: Wed, 27 Nov 1996 21:23:54 GMT
References: <1996Nov25.180454.9409@cern.ch>
Organization: MindSpring Enterprises
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In article <1996Nov25.180454.9409@cern.ch>, dcampbell@cern.ch (Diego Campbell) writes:
> Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack!

-- 
Fiona Nakamura
Tape trading list upon request. SASE required for international mail.