From ckarlsson@berkeley.edu Tue Apr 25 15:49:22 1995
Path: ashpoly!cascade!transat!sunet!nordrelay!berkeley!ckarlsson
From: ckarlsson@berkeley.edu (Camila Karlsson)
Newsgroups: comp.sys.m68k
Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Apr25.154922.5888@berkeley.edu>
Date: Tue, 25 Apr 1995 15:49:22 GMT
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.
CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot?

-- 
Camila Karlsson
Tape trading list upon request. SASE required for international mail.

From lkarlsson@uu.net Thu Apr 27 16:28:22 1995
Path: ashpoly!bigsur!pacrim!krgate!eunha!uu!lkarlsson
From: lkarlsson@uu.net (Lars Karlsson)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Apr27.162822.4450@uu.net>
Date: Thu, 27 Apr 1995 16:28:22 GMT
References: <1995Apr25.154922.5888@berkeley.edu>
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In article <1995Apr25.154922.5888@berkeley.edu>, ckarlsson@berkeley.edu (Camila Karlsson) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop.

Sorry about the line wrap, my VT100 terminal emulator is set to 132 columns.

-- 
Lars Karlsson | lkarlsson@uu.net
PGP Key fingerprint: CABA 8CBE B9D2 AF69
"Keep the channels open."