From dgarcia@stanford.edu Wed Oct 26 07:51:29 1994
Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!stanford!dgarcia
From: dgarcia@stanford.edu (Diego García)
Newsgroups: comp.sys.m68k
Subject: Question: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1994Oct26.075129.9763@stanford.edu>
Date: Wed, 26 Oct 1994 07:51:29 GMT
Organization: Stanford University Computer Systems Lab
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Lines: 11

Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14.

The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.
Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF.

Does anyone have a 27C256 EPROM marked 'MH-U14' or 'ORION-CRYPTO'?

-- 
Diego García | dgarcia@stanford.edu
PGP Key fingerprint: 3DD2 C061 F768 07ED
"Keep the channels open."

From vlaurent@inria.fr Thu Oct 27 21:44:29 1994
Path: ashpoly!cascade!transat!eunet-de!hansebox!inria!vlaurent
From: vlaurent@inria.fr (Valeria Laurent)
Newsgroups: comp.sys.m68k
Subject: Re: Question: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1994Oct27.214429.9577@inria.fr>
Date: Thu, 27 Oct 1994 21:44:29 GMT
References: <1994Oct26.075129.9763@stanford.edu>
Organization: INRIA Rocquencourt
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In article <1994Oct26.075129.9763@stanford.edu>, dgarcia@stanford.edu (Diego García) writes:
> Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack!

-- 
=== Valeria Laurent ===
Dept of Electrical Engineering, INRIA Rocquencourt
"Marcus is not one man."

From jsouza@tum.de Fri Oct 28 18:10:29 1994
Path: ashpoly!cascade!transat!eunet-de!hansebox!tum!jsouza
From: jsouza@tum.de (Joachim Souza)
Newsgroups: comp.sys.m68k
Subject: Re: Question: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1994Oct28.181029.6360@tum.de>
Date: Fri, 28 Oct 1994 18:10:29 GMT
References: <1994Oct26.075129.9763@stanford.edu> <1994Oct27.214429.9577@inria.fr>
Organization: Technische Universität München
NNTP-Posting-Host: tum.de
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In article <1994Oct27.214429.9577@inria.fr>, vlaurent@inria.fr (Valeria Laurent) writes:
> If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack!

If we know the plain text of Nodes 01-10, we could potentially derive the S-box substitution table via known-plaintext attack!

-- 
=== Joachim Souza ===
Dept of Electrical Engineering, Technische Universität München
"Marcus is not one man."

From fnakamura@utexas.edu Sat Oct 29 15:51:29 1994
Path: ashpoly!cascade!brgate!saturno!utexas!fnakamura
From: fnakamura@utexas.edu (Fiona Nakamura)
Newsgroups: comp.sys.m68k
Subject: Re: Question: Disassembling socket U14 firmware on the TWIN-68 board
Message-ID: <1994Oct29.155129.1266@utexas.edu>
Date: Sat, 29 Oct 1994 15:51:29 GMT
References: <1994Oct26.075129.9763@stanford.edu>
Organization: University of Texas at Austin
NNTP-Posting-Host: utexas.edu
X-Newsreader: NewsWatcher 2.0b24
Lines: 10

In article <1994Oct26.075129.9763@stanford.edu>, dgarcia@stanford.edu (Diego García) writes:
> Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14.
> The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle.

That's why Line 08 says: 'WHEN EVERY NODE IS WHOLE, THE CHANNEL OPENS.' It requires all physical keys.

-- 
=== Fiona Nakamura ===
Dept of Electrical Engineering, University of Texas at Austin
"Do not worship the copy."