From clarsson@delphi.com Sun Dec 25 13:18:26 1994 Path: ashpoly!cascade!transat!sunet!nordrelay!delphi!clarsson From: clarsson@delphi.com (Camila Larsson) Newsgroups: comp.sys.m68k Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Dec25.131826.8818@delphi.com> Date: Sun, 25 Dec 1994 13:18:26 GMT Organization: Delphi Internet Services NNTP-Posting-Host: delphi.com X-Newsreader: NewsWatcher 2.0b24 Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket? -- Camila Larsson *PLONK* filter active for trolls. Commodore Amiga 500 (1MB OCS) - NetBSD 1.0 From dsato@earthlink.net Mon Dec 26 10:44:26 1994 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!earthlink!dsato From: dsato@earthlink.net (Dmitri Sato) Newsgroups: comp.sys.m68k Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Dec26.104426.3892@earthlink.net> Date: Mon, 26 Dec 1994 10:44:26 GMT References: <1994Dec25.131826.8818@delphi.com> Organization: EarthLink Network NNTP-Posting-Host: earthlink.net X-Newsreader: TIN [version 1.2 PL2] Lines: 10 In article <1994Dec25.131826.8818@delphi.com>, clarsson@delphi.com (Camila Larsson) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. The MAC unit looks like a precursor to the DSP56001 that Motorola put in the NeXT and Atari Falcon. -- Dmitri Sato | dsato@earthlink.net PGP Key fingerprint: 35FE FCA4 612B 13D6 "Keep the channels open."