From agirard@netcom.com Mon Dec 02 11:22:24 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!netcom!agirard From: agirard@netcom.com (Amy Girard) Newsgroups: comp.sys.m68k Subject: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1996Dec02.112224.4274@netcom.com> Date: Mon, 02 Dec 1996 11:22:24 GMT Organization: NETCOM On-Line Communication Services NNTP-Posting-Host: netcom.com X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14. The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF. Did Marcus take the decryption EPROM with him when he left the lab? -- Amy Girard Opinions expressed are solely my own and not those of NETCOM On-Line Communication Services. ------------------------------------------------------------ From asato@pacbell.net Mon Dec 02 18:40:24 1996 Path: ashpoly!cascade!transat!eunet-fr!teletel!pacbell!asato From: asato@pacbell.net (Aiko Sato) Newsgroups: comp.sys.m68k Subject: Re: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1996Dec02.184024.1369@pacbell.net> Date: Mon, 02 Dec 1996 18:40:24 GMT References: <1996Dec02.112224.4274@netcom.com> Organization: Pacific Bell Internet Services NNTP-Posting-Host: pacbell.net X-Newsreader: NewsWatcher 2.0b24 Lines: 10 In article <1996Dec02.112224.4274@netcom.com>, agirard@netcom.com (Amy Girard) writes: > Tracing the address decoder lines on the motherboard reveals what was supposed to be in socket U14. > The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984. -- Aiko Sato "In theory there is no difference between theory and practice." Pentium 90 (OS/2 Warp) / TOS 4.04