From mduarte@uu.net Thu Dec 19 15:30:29 1996 Path: ashpoly!cascade!transat!eunet-de!hansebox!uu!mduarte From: mduarte@uu.net (Mikhail Duarte) Newsgroups: comp.sys.m68k Subject: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec19.153029.2028@uu.net> Date: Thu, 19 Dec 1996 15:30:29 GMT Organization: UUNET Technologies, Falls Church VA NNTP-Posting-Host: uu.net X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. At ROM offset 0x0909, the string 'M.H. // THE HATCH IS OPEN // ADVANCED ACOUSTICS LAB' is stored in ASCII. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Mikhail Duarte *PLONK* filter active for trolls. Sun 3/60 (SunOS 4.1.1) - NetBSD 1.0 From atanaka@berkeley.edu Sat Dec 21 06:09:29 1996 Path: ashpoly!cascade!transat!eunet-de!hansebox!berkeley!atanaka From: atanaka@berkeley.edu (Andrei Tanaka) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec21.060929.1414@berkeley.edu> Date: Sat, 21 Dec 1996 06:09:29 GMT References: <1996Dec19.153029.2028@uu.net> Organization: UC Berkeley Department of EECS NNTP-Posting-Host: berkeley.edu X-Newsreader: WinVN 0.99.5 Lines: 8 In article <1996Dec19.153029.2028@uu.net>, mduarte@uu.net (Mikhail Duarte) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. -- Andrei Tanaka -- UC Berkeley Department of EECS "A soul is not exclusive to biology." From lkuznetsov@tum.de Sat Dec 21 21:30:29 1996 Path: ashpoly!cascade!mxgate!coyoacan!tum!lkuznetsov From: lkuznetsov@tum.de (Lucia Kuznetsov) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec21.213029.2231@tum.de> Date: Sat, 21 Dec 1996 21:30:29 GMT References: <1996Dec19.153029.2028@uu.net> <1996Dec21.060929.1414@berkeley.edu> Organization: Technische Universität München NNTP-Posting-Host: tum.de X-Newsreader: WinVN 0.99.5 Lines: 9 In article <1996Dec21.060929.1414@berkeley.edu>, atanaka@berkeley.edu (Andrei Tanaka) writes: > The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space. Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop. -- Lucia Kuznetsov | lkuznetsov@tum.de PGP Key fingerprint: 57DA 1309 CF5A 83C7 "Keep the channels open." From drobertson@mindspring.com Sun Dec 22 19:24:29 1996 Path: ashpoly!cascade!bigsur!mindspring!drobertson From: drobertson@mindspring.com (Dave Robertson) Newsgroups: comp.sys.m68k Subject: Re: Question: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1996Dec22.192429.2982@mindspring.com> Date: Sun, 22 Dec 1996 19:24:29 GMT References: <1996Dec19.153029.2028@uu.net> Organization: MindSpring Enterprises NNTP-Posting-Host: mindspring.com X-Newsreader: WinVN 0.99.5 Lines: 10 In article <1996Dec19.153029.2028@uu.net>, mduarte@uu.net (Mikhail Duarte) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. > CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. -- Dave Robertson "The hatch is open. Is anyone listening?" NeXTstation Turbo Color / AmigaOS 3.1