From claurent@utexas.edu Tue Jan 24 19:22:34 1995
Path: ashpoly!bigsur!pacrim!jpgate!kamome!utexas!claurent
From: claurent@utexas.edu (Camila Laurent)
Newsgroups: comp.sys.m68k
Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jan24.192234.9489@utexas.edu>
Date: Tue, 24 Jan 1995 19:22:34 GMT
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.
Disassembling ROM #0 reveals an initialization routine that checks for a hardware dongle marked 'ORION-ENC-84'.

One 28-pin EPROM socket (labeled U14) is completely empty. What firmware was supposed to be in that socket?

-- 
Camila Laurent -- University of Texas at Austin
"They will send a copy in my place."

From bkang@utexas.edu Wed Jan 25 22:05:34 1995
Path: ashpoly!cascade!bigsur!utexas!bkang
From: bkang@utexas.edu (Bruno Kang)
Newsgroups: comp.sys.m68k
Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Jan25.220534.7850@utexas.edu>
Date: Wed, 25 Jan 1995 22:05:34 GMT
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In article <1995Jan24.192234.9489@utexas.edu>, claurent@utexas.edu (Camila Laurent) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

Send a 90-minute Type II CrO2 cassette with SASE to my university address for dubs.

-- 
Bruno Kang -- University of Texas at Austin
"We don't sign stars. We build them."