From ktakahashi@cern.ch Thu Feb 03 10:52:30 1994 Path: ashpoly!cascade!transat!ukc!fennimore!cern!ktakahashi From: ktakahashi@cern.ch (Kirsty Takahashi) Newsgroups: comp.sys.m68k Subject: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Feb03.105230.3750@cern.ch> Date: Thu, 03 Feb 1994 10:52:30 GMT Organization: European Laboratory for Particle Physics, Geneva NNTP-Posting-Host: cern.ch X-Newsreader: WinVN 0.99.5 Lines: 10 Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank. CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit. Schematic diagram in ASCII uploaded to ftp.ashford-poly.edu:/pub/telecom-archives/twin68_array.asc. -- Kirsty Takahashi Tape trading list upon request. SASE required for international mail. From emartinez@mit.edu Sat Feb 05 13:06:30 1994 Path: ashpoly!cascade!transat!sunet!nordrelay!mit!emartinez From: emartinez@mit.edu (Élodie Martínez) Newsgroups: comp.sys.m68k Subject: Re: TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump Message-ID: <1994Feb05.130630.2405@mit.edu> Date: Sat, 05 Feb 1994 13:06:30 GMT References: <1994Feb03.105230.3750@cern.ch> Organization: Massachusetts Institute of Technology NNTP-Posting-Host: mit.edu X-Newsreader: NewsWatcher 2.0b24 Lines: 11 In article <1994Feb03.105230.3750@cern.ch>, ktakahashi@cern.ch (Kirsty Takahashi) writes: > Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look. That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely. Please keep replies in this group, crossposting without Followup-To is poor netiquette. -- Élodie Martínez Hayes Optima 288 @ ISDN 64k bps "Extraordinary claims require extraordinary spectra."