From cgarcia@clari.net Fri Mar 01 18:09:36 1996 Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!clari!cgarcia From: cgarcia@clari.net (Camila García) Newsgroups: comp.sys.m68k Subject: Data: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1996Mar01.180936.7014@clari.net> Date: Fri, 01 Mar 1996 18:09:36 GMT Organization: ClariNet Communications Corp NNTP-Posting-Host: clari.net X-Newsreader: TIN [version 1.2 PL2] Lines: 11 Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Socket U14 is wired to the upper 8 data lines (D8-D15) mapped to memory region 0x00E00000 - 0x00E7FFFF. Did Marcus take the decryption EPROM with him when he left the lab? -- Camila García US Robotics Courier V.34 @ 14,400 bps "We don't sign stars. We build them." From lsokolov@panix.com Sat Mar 02 04:30:36 1996 Path: ashpoly!cascade!transat!sunet!nordrelay!panix!lsokolov From: lsokolov@panix.com (Lucia Sokolov) Newsgroups: comp.sys.m68k Subject: Re: Data: Disassembling socket U14 firmware on the TWIN-68 board Message-ID: <1996Mar02.043036.5475@panix.com> Date: Sat, 02 Mar 1996 04:30:36 GMT References: <1996Mar01.180936.7014@clari.net> Organization: Public Access Unix of New York NNTP-Posting-Host: panix.com X-Newsreader: Netscape 1.1N Lines: 9 In article <1996Mar01.180936.7014@clari.net>, cgarcia@clari.net (Camila García) writes: > Further progress on reverse-engineering the empty socket U14 on the TWIN-68 Rev C coprocessor board. > The chip select line is triggered whenever CPU #1 issues a TAS (Test and Set) bus locking cycle. Using an S-box in a 27256 EPROM for single-cycle hardware substitution was standard military cipher practice in 1984. -- Lucia Sokolov -- Public Access Unix of New York "Row 14. No joke."