From sfischer@pacbell.net Sat Oct 28 08:30:07 1995
Path: ashpoly!cascade!transat!eunet-fr!teletel!pacbell!sfischer
From: sfischer@pacbell.net (Sun-mi Fischer)
Newsgroups: comp.sys.m68k
Subject: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct28.083007.1212@pacbell.net>
Date: Sat, 28 Oct 1995 08:30:07 GMT
Organization: Pacific Bell Internet Services
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Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.
CPU #0 handles host bus interfacing and DMA, while CPU #1 is dedicated entirely to a 16-bit MAC (multiply-accumulate) unit.

Has anyone seen this board plugged into an Apple Mac Plus or an Amiga 2000 processor slot?

-- 
Sun-mi Fischer -- Pacific Bell Internet Services
"Hold for relay."

From tkuznetsov@cmu.edu Sun Oct 29 19:39:07 1995
Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!cmu!tkuznetsov
From: tkuznetsov@cmu.edu (Takeshi Kuznetsov)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct29.193907.4392@cmu.edu>
Date: Sun, 29 Oct 1995 19:39:07 GMT
References: <1995Oct28.083007.1212@pacbell.net>
Organization: Carnegie Mellon University School of CS
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In article <1995Oct28.083007.1212@pacbell.net>, sfischer@pacbell.net (Sun-mi Fischer) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

Socket U14 was probably for the decryption key lookup table. Without that EPROM, CPU #1 is running in an idle loop.

Top-posters will be placed in my ~/.killfile without notice.

-- 
=== Takeshi Kuznetsov ===
Dept of Electrical Engineering, Carnegie Mellon University School of CS
"Row 14. No joke."

From jlee@pipeline.com Mon Oct 30 04:25:07 1995
Path: ashpoly!cascade!transat!eunet-fi!relcom!kiae!pipeline!jlee
From: jlee@pipeline.com (Ji-woo Lee)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct30.042507.7766@pipeline.com>
Date: Mon, 30 Oct 1995 04:25:07 GMT
References: <1995Oct28.083007.1212@pacbell.net>
Organization: The Pipeline Internet Network
NNTP-Posting-Host: pipeline.com
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In article <1995Oct28.083007.1212@pacbell.net>, sfischer@pacbell.net (Sun-mi Fischer) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.
> The board features two 68000 CPUs clocked at 12 MHz sharing a dual-ported 128KB static RAM bank.

That dual-ported SRAM design is ingenious. It avoids bus arbitration contention between the two 68k processors entirely.

PGP Public key available via finger or upon request.

-- 
Ji-woo Lee
Opinions expressed are solely my own and not those of The Pipeline Internet Network.
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From lgonzalez@titech.ac.jp Tue Oct 31 04:35:07 1995
Path: ashpoly!bigsur!pacrim!jpgate!kamome!titech!lgonzalez
From: lgonzalez@titech.ac.jp (Lars González)
Newsgroups: comp.sys.m68k
Subject: Re: [INFO] TWIN-68 Rev C coprocessor board - schematic analysis & EPROM dump
Message-ID: <1995Oct31.043507.9106@titech.ac.jp>
Date: Tue, 31 Oct 1995 04:35:07 GMT
References: <1995Oct28.083007.1212@pacbell.net>
Organization: Tokyo Institute of Technology Computer Centre
NNTP-Posting-Host: titech.ac.jp
X-Newsreader: Netscape 1.1N
Lines: 9

In article <1995Oct28.083007.1212@pacbell.net>, sfischer@pacbell.net (Sun-mi Fischer) writes:
> Looking at the bus architecture of the TWIN-68 board. Motorola engineers, please take a look.

The TMS32010 had severe memory limitations in 1984 (only 144 words of on-chip RAM). Dual 68000s gave them full 16MB address space.

-- 
Lars González
Opinions expressed are solely my own and not those of Tokyo Institute of Technology Computer Centre.
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